1. Field of the Invention
The present invention relates to a high-speed complementary pass-transistor logic (referred to as “CPL”, hereinafter).
2. Description of Related Art
Currently, CMOS logic is in vogue for semiconductor logic circuit. It is important to decrease the supply voltage of the CMOS logic for reducing power consumption, since power consumption is proportional to a square of power supply voltage in CMOS logic circuit.
A variety of circuit technologies have been proposed in which the operation speed is enhanced with a low supply voltage, since reducing the supply voltage causes a reduction of operation speed. Among them, there is a CPL in which a desired logic operation is provided using N-channel MOS transistors (referred to as “NMOSs”, hereinafter) as signal transmission passes so as to configure a logic network.
FIG. 2 is a configuration diagram illustrating a logical product gate comprised of a conventional CPL (referred to as “AND gate” or “AND”, hereinafter), which is described in IEEE JOURNAL OF SOLID-STATE CIRCUITS, 25[2] (1990-4), pages. 388-395 entitled “A 3.8 ns CMOS 16×16-b Multiplier Using Complementary Pass-Transistor Logic”.
The AND gate comprised of the CPL has input nodes I1 and I4 provided with complementary input signals “a” and “/a” (hereinafter, simply denoted as a and /a), input nodes I2 and I3 provided with complementary input signals “b” and “/b” (hereinafter, simply denoted as b and /b), and a pair of intermediate nodes M1 and M2 outputting complementary intermediate signals “m” and “/m” (hereinafter, simply denoted as m and /m). A signal transmission path comprised of a plurality of NMOSs is arranged between the input nodes and the intermediate nodes and is connected as a logic network for performing a desired logic operation. In the case of the AND, for example, NMOSs 1 and 2 are connected between the input nodes I1 and I2 and the intermediate node M1, respectively, and gates of the NMOS 1 and 2 are provided with complementary input signals b and /b, respectively. Further, NMOSs 3 and 4 are connected between input nodes I3 and I4 and the intermediate node M2, respectively, and gates of the NMOS 3 and 4 are also provided with the complementary input signals /b and b, respectively.
The intermediate nodes M1 and M2 are connected to CMOS inverters 5 and 6, respectively, which invert the intermediate signals m and /m, so that complementary output signals /a·b and a·b having desired logic levels are output from output nodes O1 and O2.
Hereinafter, a description will be given of an operation of the logic gate.
For example, when the input signals a and b have levels “H” and “L”, respectively, the NMOSs 1 and 4 are in an OFF state, and the NMOSs 2 and 3 are in an ON state. In this case, the intermediate node M1 is connected to level “L” (that is, a ground potential) through the NMOS 2 and the intermediate node M2 is connected to level “H” (that is, a supply potential) through the NMOS 3. Accordingly, the intermediate signals m and /m are at levels “L” and “H”, respectively. The intermediate signals m and /m are further inverted by the CMOS inverters 5 and 6, so that output signals having desired logic levels “H” and “L” based on the supply potential are output from the output nodes O1 and O2.
Here, it is assumed that the input signal b is changed from “L” to “H”.
According to the change of the input signal b, the NMOSs 1 and 4 are changed from the OFF state to the ON state, and the NMOSs 2 and 3 are changed from the OFF state to the ON state. By this, the intermediate node M1 is connected to the input node I1 at level “H” through the NMOS 1, so that charge for the intermediate node M1 is started. On the other hand, the intermediate node M2 is connected to the input node I4 at level “L” through the NMOS, so that discharge for the intermediate M2 is started. The charge and discharge operations for the intermediate nodes M1 and M2 are started at a timing when the input signal b rises to about threshold voltage of the NMOSs 1 and 4 (for example, 0.2V). Further, when one of the intermediate nodes M1 and M2 is discharged, the other is charged.
As such, since the level changes of the intermediate nodes start when the input signal is at about the threshold voltage of the NMOS in the CPL, the operation speed can be enhanced compared with the conventional COMS logic circuit whose logic threshold voltage is ½ of the supply voltage.
Although one NMOS is connected between the input node and the intermediate node in the above-described CPL, when a 3-input type AND or complicated logic is configured as the CPL, two or more NMOSs should be serially connected between the input node and the intermediate node of the logic network. Therefore, there occurs a problem in that on-resistance between the input node and the intermediate node is increased, and accordingly the charge and discharge operations are delayed. Further, there is a problem in that when the inverters, which convert the intermediate signals m and /m of the intermediate nodes into desired levels to generate output signals, do not operate at a high-speed, it is not possible to operate the entire circuit at a high-speed.